FPGA IP CORES
Intellectual Property Cores for Wide Range of Video Formats and Standards
The HEVC 4K Decoder Core by VYUsync is a highly optimized video decompression engine targeted primarily at FPGAs. The decoder achieves real-time performance for 4K ultra high definition (UHD) video with ultra-low latency & optimized resource utilization. It iswell suited for various applications ranging from broadcastand professional video to high end consumer electronics.
The decoder design is fully autonomous and does notrequire any external processor to aid the decode operation.The IO interface comprises of an input FIFO and an outputframe buffer. Decoded data can also be provided on a serialbus with embedded sync information. The decoder requiresDDR SDRAM to store reference pictures.
The decoder solution is available either as a FPGA netlist orin source code format and can be customized to meet therequirements of end users.
Please click here to download the datasheet
HEVC 4K decoder is fully compliant with the ISO/ IEC 23008-2 standard and ITU-T H.265 standard. The HEVC 4K Decoder has been validated in hardware using conformance streams from ITU-T & other Industry standard test suites for functional and performance testing. It is a universal decoder.
This IP is filed, tested and proven in various customer applications. VYUsync’s HEVC decoder IP core is evaluated & purchased by leaders in Broadcasting Industry. The HEVC 4K decoder supports all the features which are part of the H.265 standard with respect to the Profiles listed.
The HEVC 4K Decoder is an Ultra-low latency decoder with robust error handling & resilience. It support Monochrome, Monochrome 12, Main, Main 10, Main 12, Main 4:2:2 10, and Main 4:2:2 12 profiles that allows for a bit depth of 8-bits to 12-bits per sample with support for 4:0:0, 4:2:0, and 4:2:2 Chroma sampling.
The HEVC 4K decoder is capable of decoding all the bit streams that are encoded for the High Tier & Level 4.1 and for all lower tiers/Levels. The HEVC 4K decoder supports 75Mbps bitrate with an option to scale up to 150Mbps. The decoder decodes at the rate of 60 Frames per second.
The video formats supported by the HEVC 4k decoder are .NTSC, PAL, 720p50, 720p59.94 720p60, 1080i50, 1080i59.94, 1080i60, 1080Psf25, 1080Psf29.97, 1080Psf30 1080p23.98, 1080p24, 1080p25, 1080p29.97, 1080p30, 1080p50, 1080p59.94, 1080p60, 4Kp23.98, 4Kp24, 4Kp25, 4Kp29.97, 4Kp30, 4Kp50, 4Kp59.94, 4Kp60.
All the non-standard resolutions are supported by the decoder up to a maximum resolution of 4096x2160 and a maximum frame rate of 60. For example, monitor resolution 1600x900, 1600 x 1200, 1920 x 1440, 1920 x 1200 is supported.
The IO interface comprises of an input FIFO and an output frame buffer. The HEVC 4K decoder accepts Elementary stream in Annex B Byte stream format. There is also an option for accepting Transport stream input when coupled with Transport Stream Demultiplexer IP.
The decoder requires DDR SDRAM to store reference pictures. The decoded pixels are written to DDR4 memory and decoded picture properties are signaled to the external system. The decoded data can also be provided in YUV data with embedded sync information.
The HEVC 4k decoder can be implemented in the Xilinx Kintex Ultrascale KU060. A feature constrained version of the decoder can also be implemented in the Xilinx Kintex Ultrascale KU040 FPGA. The HEVC 4K decoder on Intel Altera Arria 10 will be available on customers request.
FPGA resources utilization for 3840x2160p60, 422, 10-bit, 75 mbps decoder is LUT’s -105000, BRAM’s – 381 & DSP’s – 900. This does not include memory controller, display controller & TS demultiplexer and requires a total of 80+80+48 bit = 208 bit external memory running at 1000MHz.