FPGA IP CORES
Intellectual Property Cores for Wide Range of Video Formats and Standards
The XAVC Encode Decode solution is a high performance & highly optimized video compression-decompression engine targeted primarily at FPGAs. It is complaint with ISO/IEC 14496-10 and ITU-T H.264 standard. It is well suited for various applications ranging from broadcast & professional video to high end consumer electronics.
The Codec design is fully autonomous and does not require any external processor to aid the codec operations. The encoder takes in the uncompressed video input and outputs encoded video in Elementary Stream (ES) format or optionally in Transport Stream (TS) format. The decoder takes in the ES/ TS & output is 80-bit YUV data with embedded sync.
The codec solution is available either as a FPGA netlist or in source code format and can be customized to meet the requirement of end customer.
Please click here to download the datasheet